As circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 45 nm and 32 nm dimensions, whereas the thickness of the dielectric layers remain substantially constant, with the result of increasing the aspect ratios of the features. In order to enable fabrication of next generation devices and structures, three dimensional (3D) stacking of semiconductor chips is often utilized to improve performance of the transistors. By arranging transistors in three dimensions instead of conventional two dimensions, multiple transistors may be placed in the integrated circuits (ICs) very close to each other. Three dimensional (3D) stacking of semiconductor chips reduces wire lengths and keeps wiring delay low. In manufacturing three dimensional (3D) stacking of semiconductor chips, stair-like structures are often utilized to allow multiple interconnection structures to be disposed thereon, forming high-density of vertical transistor devices.
As the density of devices stacked vertically increases, the aspect ratio of features correspondingly increases. Along with the increase in aspect ratios, it becomes more difficult to achieve a uniform etch profile. One traditional approach for achieving a uniform etch profile is the use of a multi-operation etch recipe. The first operation opens the sidewalls followed by subsequent operations of high-energy bombardment to form a straight wall having a uniform etch profile. However, as aspect ratios increase it has become more difficult to achieve a uniform etch profile using traditional multi-operation etch recipes. In another traditional approach a single operation etch recipe with very high ion bombardment is used to provide an anisotropic etch. However, the high energies needed to achieve a straight etch profile using traditional one-step etch recipes leads to plasma damage on the top surface of the structure.
Therefore, there is a need for additional methods for achieving uniform etch profiles.